Generally, a semiconductor device (e.g., a metal oxide semiconductor (MOS) transistor) includes source/drain regions in a silicon substrate. A gate insulation layer is formed on the silicon substrate between the source/drain regions. A gate is formed on the gate insulation layer. Accordingly, when an electric field is applied to the gate, carriers move through a channel formed in the silicon substrate under the gate insulation layer and thereby enable the semiconductor device to be turned on and off.
According to a known semiconductor device, such a gate is typically formed to be planar. When the gate is planarly formed, it may act as a limitation on higher integration of semiconductor devices. That is, when semiconductor devices are designed only planarly, integration may be limited due to the limited available area.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.